1. Field of the Invention
The present invention relates to a MOS transistor, and more particularly, to a MOS transistor with two empty side slots on its gate and its method of formation.
2. Description of the Prior Art
Use of MOS transistors has become a very common practice in the semiconductor industry. There are usually an inordinately high number of MOS transistors on a semiconductor chip. This has led to keen interest in finding effective ways of producing smaller transistors with improved electrical characteristics. Please refer to FIG. 1. FIG. 1 is a sectional diagram of a transistor 10 according to the prior art. The transistor 10 comprises a rectangular gate 14, a drain 16, and a source 18. The gate 14 comprises a conducting layer 15, a metallic silicide layer 20, and two spacers 17 at two sides of the gate 14. Each of the drain 16 and the source 18 comprises a high density doped layer 21, 23, a high doped drain/low doped drain (HDD/LDD) layer 25,27 and a metallic silicide layer 22, 24. Trenches 12 are used to isolate the transistor 10 from other components on the substrate 11 of a semiconductor wafer.
Despite the popularity of the above described transistor structure, problems arise when manufacturing small sized transistors that are less than 0.18 um in size. These problems include:
1. Increase in the cost of a lithographic stepper: Deep UV is the light source in the lithography stepper but interference and diffraction occur with this light source when transistors of less than 0.18 um are processed. Changing to a light source with a reduced wavelength of light may alleviate the problem but this increases costs as well.
2. Difficulty in the formation of metallic silicide: The metallic silicide layers 20, 22, 24 are used to reduce the conductive resistance of the gate 14, drain 16 and source 18 and are formed by reacting metal and silicon on the semiconductor wafer. A common practice is to form Ti-silicide by reacting titanium with the silicon on surfaces of the gate 14, drain 16 and source 18. The reaction requires a certain minimum surface area of silicon. However, At sizes of 0.18 um or less, it becomes exceedingly difficult to form metallic silicide due to insufficient surface area.
It is therefore a primary objective of the present invention to provide a MOS transistor with two empty side slots on its gate and method for its formation to solve the above mentioned problems.
In a preferred embodiment, the present invention provides a MOS (metal-oxide-semiconductor) transistor comprising:
a substrate having a surface layer which comprises a drain and a source separately positioned on two separate areas of the surface layer;
an insulation layer positioned on the surface of the substrate between the drain and the source;
a gate comprising:
a conducting layer positioned on the insulation layer having a bottom side, a top side, a left side and a right side; and
a metallic silicide layer positioned on the top side of the conducting layer for reducing resistance of the conducting layer wherein the width of the metallic silicide layer is greater than that of the bottom side of the conducting layer; and
a dielectric layer covered on the drain, the source and the metallic silicide layer;
wherein the transistor comprises at least one side slot positioned between the dielectric layer and the left side or right side of the conducting layer below the metallic silicide layer.
It is an advantage of the present invention that the method for forming the transistor according to the present invention can produce smaller transistors possessing many electrical advantages making this method ideal for processing semiconductors under 0.18 um.
This and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.